// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hiddrphy_ac_static_reg_reg_offset.h
// Project line  :  IP
// Department    :  
// Author        :  Jason, Edward
// Version       :  .1
// Date          :  2011/11/29
// Description   :  The DDR PHY Controller Block
// Others        :  Generated automatically by nManager V4.2 
// History       :  Jason, Edward 2018/03/19 12:28:13 Create file
// ******************************************************************************

#ifndef __HIDDRPHY_AC_STATIC_REG_REG_OFFSET_H__
#define __HIDDRPHY_AC_STATIC_REG_REG_OFFSET_H__

/* HIDDRPHY_AC_STATIC_REG Base address of Module's Register */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE                       (0x1000)

/******************************************************************************/
/*                      PHY_Controller HIDDRPHY_AC_STATIC_REG Registers' Definitions                            */
/******************************************************************************/

#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PLLCTRL_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x10) /* This register specified the timing paramters for PLL in both address /command, and data block. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PHYCTRL0_REG            (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x14) /* PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL_REG               (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x18) /* IO control register */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PHYCTRL1_REG            (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x1C) /* AC PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PHYPLLCTRL_AC_REG       (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x20) /* PHY PLL control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PHYCTRL2_REG            (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x24) /* AC PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL2_REG              (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x28) /* PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PHYPLLCTRL_DX3_REG      (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x2C) /* PHY PLL control register 3 */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PHYCTRL3_REG            (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x30) /* AC PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PHYCTRL4_REG            (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x34) /* AC PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACCMDBDL0_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x38) /* AC command bit delay line setting */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_PHYCTRL5_REG            (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x3C) /* AC PHY control registers Register in this field are connected to PHY interface directly */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACCMDBDL4_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x48) /* AC command bit delay line setting */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACCLKBDL_REG            (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x50) /* AC clock bit delay line setting */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL0_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x54) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL1_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x58) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL2_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x5C) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL3_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x60) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL4_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x64) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL5_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x68) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL6_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x6C) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL7_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x70) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACDEBUG_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x74) /* This register is for PHY debug only. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYRSVDC_REG          (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x78) /* AC block PHY reserved control pins. This register is for PHY control and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYRSVDS_REG          (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x7C) /* AC block PHY reserved control pins. This register is for PHY control and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYDCC_REG            (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x94) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL9_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x98) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL10_REG          (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x9C) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYCTL11_REG          (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xA0) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL3_REG              (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xA4) /* IO control register */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYDCC1_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xAC) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACPHYDCC2_REG           (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xB0) /* AC block PHY control register. This register is for PHY control, and should not be modified. */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL5_REG              (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xB4) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL6_REG              (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xB8) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL7_REG              (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xA8) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL8_REG              (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xDC) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL9_REG              (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xBC) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL10_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xC0) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL11_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xC4) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL12_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xC8) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL13_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xCC) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL14_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xD0) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL15_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xD4) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL16_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xD8) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL18_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x40) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL19_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x44) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL20_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0x4C) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_BYP_CK90_SETTING_REG    (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xE4) /* SELECT CK90 delay line value */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_BDL_SW_RST_REG          (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xE8) /* DBL Software rest */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACCTL_PHASE_REG         (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xEC) /* Phase Selection */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_IOCTL17_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xF0) 
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACRSVD1_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xF4) /* AC RSVD register1 */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_ACRSVD2_REG             (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xF8) /* AC RSVD register2 */
#define PHY_Controller_HIDDRPHY_AC_STATIC_REG_AC_DDRPHY_GATED_BYPASS_REG (PHY_Controller_HIDDRPHY_AC_STATIC_REG_BASE + 0xFC) /* bypass clock gated function */

#endif // __HIDDRPHY_AC_STATIC_REG_REG_OFFSET_H__
